微處理器 - Lattice LCMXO2-1200HC-4MG132C (STEP-MXO2 V1.1) - VHDL - Button


參考資訊：
https://www.stepfpga.com/doc/step-mxo2%E5%85%A5%E9%97%A8%E6%95%99%E7%A8%8B

top.vhd 

library ieee;
use ieee.std_logic_1164.all;
     
entity main is
    port(
        clk : in std_logic;
        btn : in std_logic;
        led : out std_logic
    );
end main;
     
architecture logic of main is
begin
    process(btn) is
    begin
        led <= btn;
    end process;
end logic;

top.lpf 

LOCATE COMP "led" SITE "A7";
LOCATE COMP "btn" SITE "B7";
LOCATE COMP "clk" SITE "C1";

Makefile 

all:
	yosys -m ghdl -p "ghdl top.vhd -e main; synth_lattice -family xo2 -json top.json"
	nextpnr-machxo2 --device LCMXO2-1200HC-4MG132C --lpf top.lpf --json top.json --textcfg top.txt
	ecppack --compress top.txt top.bit --jed top.jed

ram:
	openFPGALoader -b step-mxo2_v1.1 top.bit

flash:
	openFPGALoader -b step-mxo2_v1.1 top.jed

clean:
	rm -rf top.txt top.bit top.json top.jed

編譯、下載 

$ make
$ make ram

完成