微處理器 - Gowin GW1NSR-LV4CQN48PC6/I5 (Lichee Tang Nano 4K) - Verilog - Button

main.v

module main (
    input btn,
    output reg led
);

initial begin
    led = 0;
end
  
always @(posedge btn) begin
    led <= ~led;
end
 
endmodule

main.cst

IO_LOC "led" 10;
IO_LOC "btn" 14;

完成