參考資訊:
https://github.com/YosysHQ/apicula/tree/master/examples
https://github.com/YosysHQ/apicula/wiki/Nextpnr%E2%80%90Himbaechel-Gowin
main.vhd
library ieee;
use ieee.std_logic_1164.all;
entity main is
port(
btn : in bit;
led : out bit
);
end main;
architecture logic of main is
begin
led <= btn;
end logic;
main.cst
IO_LOC "led" 15; IO_LOC "btn" 87;
完成
