微處理器 - Gowin GW2AR-LV18QN88C8/I7 (Lichee Tang Nano 20K) - Verilog - Button

參考資訊：
https://github.com/YosysHQ/apicula/tree/master/examples
https://github.com/YosysHQ/apicula/wiki/Nextpnr%E2%80%90Himbaechel-Gowin

main.v

module main (
    input btn,
    output reg led
);
  
initial begin
    led = 0;
end
    
always @(posedge btn) begin
    led <= ~led;
end
   
endmodule

main.cst

IO_LOC "led" 15;
IO_LOC "btn" 87;

完成