Steward

分享是一種喜悅、更是一種幸福

微處理器 - Lattice iCE40UP5K-SG48I (ICE40_FPGA_PICO) - Verilog - LED

---

參考資訊：
https://github.com/375432636/bin2rbt

LED腳位


top.v

module top (
    input  wire clk,
    output wire led
);

    reg [23:0] counter = 24'd0;

    always @(posedge clk) begin
        counter <= counter + 1'b1;
    end

    assign led = counter[23];

endmodule

top.pcf

set_io clk 35
set_io led 39

Makefile

all:
	yosys -p "read_verilog top.v; synth_ice40 -top top -json top.json"
	nextpnr-ice40 --up5k --package sg48 --json top.json --pcf top.pcf --asc top.asc
	icepack top.asc top.bin
	python3 bin2rbt.py --binfile top.bin --rbtfile top.rbt

clean:
	rm -f top.json top.asc top.bin top.rbt

編譯

$ make

將top.rbt複製到新增的隨身碟即可