微處理器 - Altera Cyclone IV EP4CE6E22C8N - VHDL - LED

main.vhd

library ieee;
use ieee.std_logic_1164.all;
    
entity main is
    port(
        clk : in std_logic;
        led : out std_logic
    );
end main;
    
architecture logic of main is
    signal val: std_logic;
    signal clk_cnt : integer := 0;
    
begin
    process(clk) is
    begin
        if (clk'event and clk = '1') then
            clk_cnt <= clk_cnt + 1;
  
            if (clk_cnt = 25000000) then
                clk_cnt <= 0;
                led <= val;
                val <= not val;
            end if;
        end if;
    end process;
end logic;

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