(ARM Cortex-A7) V3S (Lichee Pi Zero)
如何將uboot的輸出訊息轉到UART1
diff
diff -Naur old/arch/arm/dts/sun8i-v3s.dtsi new/arch/arm/dts/sun8i-v3s.dtsi
--- old/arch/arm/dts/sun8i-v3s.dtsi 2018-08-10 17:52:18.083552923 +0800
+++ new/arch/arm/dts/sun8i-v3s.dtsi 2018-08-10 16:35:27.183862902 +0800
@@ -214,6 +214,12 @@
bias-pull-up;
};
+ uart1_pins_a: uart1@0 {
+ pins = "PE21", "PE22";
+ function = "uart1";
+ bias-pull-up;
+ };
+
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
diff -Naur old/arch/arm/dts/sun8i-v3s-licheepi-zero.dts new/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
--- old/arch/arm/dts/sun8i-v3s-licheepi-zero.dts 2018-08-10 17:52:18.083552923 +0800
+++ new/arch/arm/dts/sun8i-v3s-licheepi-zero.dts 2018-08-10 17:22:13.042186451 +0800
@@ -50,11 +50,13 @@
aliases {
serial0 = &uart0;
+ serial1 = &uart1;
spi0 = &spi0;
};
+ /*stdout-path = "serial0:115200n8";*/
chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial1:115200n8";
};
};
@@ -76,6 +78,12 @@
pinctrl-names = "default";
status = "okay";
};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
&usb_otg {
dr_mode = "otg";
diff -Naur old/arch/arm/include/asm/arch-sunxi/gpio.h new/arch/arm/include/asm/arch-sunxi/gpio.h
--- old/arch/arm/include/asm/arch-sunxi/gpio.h 2018-08-10 17:52:18.166554175 +0800
+++ new/arch/arm/include/asm/arch-sunxi/gpio.h 2018-08-09 20:18:33.039821806 +0800
@@ -164,6 +164,7 @@
#define SUN8I_A83T_GPB_UART0 2
#define SUN8I_V3S_GPB_UART0 3
#define SUN50I_GPB_UART0 4
+#define SUN8I_V3S_GPE_UART1 4
#define SUNXI_GPC_NAND 2
#define SUNXI_GPC_SPI0 3
diff -Naur old/arch/arm/mach-sunxi/board.c new/arch/arm/mach-sunxi/board.c
--- old/arch/arm/mach-sunxi/board.c 2018-08-10 17:52:18.295556120 +0800
+++ new/arch/arm/mach-sunxi/board.c 2018-08-09 20:18:33.042816530 +0800
@@ -114,6 +114,10 @@
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I_V3S)
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(21), SUN8I_V3S_GPE_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(22), SUN8I_V3S_GPE_UART1);
+ sunxi_gpio_set_pull(SUNXI_GPE(22), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
diff -Naur old/include/configs/sun8i.h new/include/configs/sun8i.h
--- old/include/configs/sun8i.h 2018-08-10 17:52:19.868579845 +0800
+++ new/include/configs/sun8i.h 2018-08-09 20:18:33.500010990 +0800
@@ -27,6 +27,14 @@
#define CONFIG_SUNXI_USB_PHYS 2
#endif
+#define CONFIG_BOOTCOMMAND "sf probe 0; " \
+ "sf read 0x41800000 0x100000 0x10000; " \
+ "sf read 0x41000000 0x110000 0x400000; " \
+ "bootz 0x41000000 - 0x41800000"
+
+#define CONFIG_BOOTARGS "console=ttyS1,115200 earlyprintk panic=5 rootwait " \
+ "mtdparts=spi32766.0:1M(uboot)ro,64k(dtb)ro,4M(kernel)ro,-(rootfs) root=31:03 rw rootfstype=jffs2"
+
/*
* Include common sunxi configuration where most the settings are
*/
diff -Naur old/include/configs/sunxi-common.h new/include/configs/sunxi-common.h
--- old/include/configs/sunxi-common.h 2018-08-10 17:52:19.868579845 +0800
+++ new/include/configs/sunxi-common.h 2018-08-10 16:46:48.887623177 +0800
@@ -274,16 +274,18 @@
#endif
#ifndef CONFIG_CONS_INDEX
-#define CONFIG_CONS_INDEX 1 /* UART0 */
+#define CONFIG_CONS_INDEX 2 /* UART1 */
#endif
#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
-#if CONFIG_CONS_INDEX == 1
+#if CONFIG_CONS_INDEX == 1 /* UART0 */
#ifdef CONFIG_MACH_SUN9I
#define OF_STDOUT_PATH "/soc/serial@07000000:115200"
#else
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200"
#endif
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) /* UART1 */
+#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)