參考資訊:
https://github.com/AndresNavarro82/vt52-fpga-ax2
https://github.com/danderson/ulxs/blob/main/lpf.md
https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/synth_lattice.html
main.v
module main ( input clk, output reg led ); reg [23:0] clk_cnt; always @(posedge clk) begin if (clk_cnt == 24'd10000000) clk_cnt <= 24'd0; else clk_cnt <= clk_cnt + 1; if (clk_cnt == 24'd10000000) led <= ~led; end endmodule
main.lpf
LOCATE COMP "led" SITE "27"; LOCATE COMP "clk" SITE "28";
Makefile
all: yosys -p "synth_lattice -family xo2 -json main.json" main.v nextpnr-machxo2 --device LCMXO2-1200HC-4SG32C --lpf main.lpf --json main.json --textcfg main.txt ecppack --compress main.txt main.bit --jed main.jed clean: rm -rf main.txt main.bit main.json