微處理器 - Anlogic EG4S20BG256 (Lichee Tang Primer) - 如何透過yosys、td編譯程式

參考資訊：
https://git.uni-paderborn.de/circa/yosys/-/tree/master/examples/anlogic?ref_type=heads

main.v

module main(clk, led);
     
input clk;
output reg led;
reg [25:0] clk_cnt;
  
initial begin
    led = 0;
    clk_cnt = 0;
end
   
always @(posedge clk) begin
    clk_cnt = clk_cnt + 1;
    if (clk_cnt > 24000000) begin
        clk_cnt = 0;
        led = ~led;
    end
end
endmodule

main.adc

set_pin_assignment { clk } { location = k14; }
set_pin_assignment { led } { location = r3;  }

main.ys

read_verilog main.v
synth_anlogic -top main
write_verilog full.v

build.tcl

import_device eagle_s20.db -package BG256
read_verilog full.v -top main
read_adc main.adc
optimize_rtl
map_macro
map
pack
place
route
report_area -io_info -file main_phy.area
bitgen -bit main.bit -version 0X0000 -svf main.svf -svf_comment_on -g ucode:00000000000000000000000000000000

編譯

$ yosys main.ys
$ /opt/td/bin/td build.tcl

P.S. 需要依賴Anlogic TD