微處理器 - Gowin GW1NZ-LV1QN48C6/I5 (Lichee Tang Nano 1K) - Verilog - Button

參考資訊：
https://github.com/sifferman/tangnano_example
https://github.com/racerxdl/tangnano-yosys-hello

main.vhd

library ieee;
use ieee.std_logic_1164.all;
    
entity main is
    port(
        btn : in bit;
        led : out bit
    );
end main;
    
architecture logic of main is
begin
    led <= btn;
end logic;

main.cst

IO_LOC "led" 9;
IO_LOC "btn" 44;

完成