微處理器 - Gowin GW1NZ-LV1QN48C6/I5 (Lichee Tang 1K) - Verilog - LED

參考資訊：
https://github.com/sifferman/tangnano_example
https://github.com/racerxdl/tangnano-yosys-hello

main.v

module main (
    input clk,
    output reg led
);
  
reg [23:0] clk_cnt;
  
always @(posedge clk) begin
    if (clk_cnt == 24'd10000000)
        clk_cnt <= 24'd0;
    else
        clk_cnt <= clk_cnt + 1;
 
    if (clk_cnt == 24'd10000000)
        led <= ~led;
end
  
endmodule

main.cst

IO_LOC "led" 9;
IO_LOC "clk" 47;

Makefile

all:
	yosys -p "synth_gowin -json main.json -top main" main.v
	nextpnr-gowin --json main.json --write main.pack --device GW1NZ-LV1QN48C6/I5 --cst main.cst
	gowin_pack -d GW1NZ-1 -o main.fs main.pack

run:
	openFPGALoader -b tangnano1k main.fs

clean:
	rm -f *.json *.fs *.pack

編譯、下載

$ make
$ make run

完成