微處理器 - Gowin GW1NZ-LV1QN48C6/I5 (Lichee Tang 1K) - Verilog - Button

參考資訊：
https://github.com/sifferman/tangnano_example
https://github.com/racerxdl/tangnano-yosys-hello

main.v

module main (
    input btn,
    output reg led
);
 
initial begin
    led = 0;
end
   
always @(posedge btn) begin
    led <= ~led;
end
  
endmodule

main.cst

IO_LOC "led" 9;
IO_LOC "btn" 44;

完成