微處理器 - Lattice iCE40LP1K-CM36 (iCESugar-nano) - Verilog - Button

main.v

module main (
    input btn,
    output reg led
);
  
initial begin
    led = 0;
end
    
always @(posedge btn) begin
    led <= ~led;
end
   
endmodule

main.pcf

set_io led B6
set_io btn E3

完成