微處理器 - 硬體 - LCD Timing(VBPD、VFBD、VSPW、HBPD、HFPD、HSPW)

參考資訊：
http://www.programering.com/a/MTM5IzMwATI.html
https://www.fs-net.de/assets/download/docu/common/en/display_settings_from_datasheet.pdf

時序


VBPD(vertical back porch)

Said at the start of an image, invalid row vertical synchronization signal after the number, the corresponding drive in upper_margin

VFBD(vertical front porch)

Said in a frame image after the end, invalid row vertical synchronization signal before the number, the corresponding drive in lower_margin

VSPW(vertical sync pulse width)

Said vertical sync pulse width, calculated by the number of lines, the corresponding drive in vsync_len

HBPD(horizontal back porch)

Said a number from a horizontal synchronization signal to the data line between the start of VCLK, the corresponding drive in left_margin

HFPD(horizontal front porth)

The number of valid data indicates the end of a line to a horizontal synchronization signal between the start of VCLK, the corresponding drive in right_margin

HSPW(horizontal sync pulse width)

Horizontal sync pulse width, calculated using VCLK, the corresponding drive in hsync_len

計算方式

hsw + blw + (width * vsw) + elw
50  + 70  + (320   * 1)   + 10 = 360

bfw + high + efw
5   + 240  + 5 = 250

Clocks = 360*250*60 = 5400000