F1C200S >> Assembly

Timer0

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參考資料：
1. pdf
2. lichee
3. mangopi_r
4. allwinner

Work Flow


暫存器


中斷


Timer0時間

Ticks = LOSC/(TMR0_CLK_PRES*TMR0_INTV_VALUE_REG) = 32KHz/(128*256) = 1Hz

main.s

  .global _start
 
  .equiv GPIO_BASE,  0x01c20800 
  .equiv TIMER_BASE, 0x01c20c00
  .equiv INTC_BASE,  0x01c20400
 
  .equiv PA,         (0x24 * 0)
  .equiv PORT_CFG0,  0x00
  .equiv PORT_DATA,  0x10
 
  .equiv INTC_BASE_ADDR_REG, 0x04
  .equiv INTC_PEND_REG0,     0x10
  .equiv INTC_PEND_REG1,     0x14
  .equiv INTC_EN_REG0,       0x20
  .equiv INTC_EN_REG1,       0x24
  .equiv INTC_MASK_REG0,     0x30
  .equiv INTC_MASK_REG1,     0x34
  .equiv INTC_RESP_REG0,     0x40
  .equiv INTC_RESP_REG1,     0x44
  .equiv INTC_FF_REG0,       0x50
  .equiv INTC_FF_REG1,       0x54
 
  .equiv TMR_IRQ_EN_REG,      0x00
  .equiv TMR_IRQ_STA_REG,     0x04
  .equiv TMR0_CTRL_REG,       0x10
  .equiv TMR0_INTV_VALUE_REG, 0x14
  .equiv TMR0_CUR_VALUE_REG,  0x18
 
  .arm
  .text
_start:
  .long 0xea000016
  .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
  .long 0, __spl_size
  .byte 'S', 'P', 'L', 2
  .long 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
    
_vector:
  b reset
  b .
  b .
  b .
  b .
  b .
  ldr pc, _irq
  b .
 
_irq: .word irq_handler
 
irq_handler:
  ldr r0, =GPIO_BASE
  ldr r1, =0x00
  str r1, [r0, #(PA + PORT_DATA)]
  subs pc, lr, #4
 
reset:
  mrc p15, 0, r0, c1, c0, 0
  bic r0, #(1 << 13)
  mcr p15, 0, r0, c1, c0, 0
 
  adr r0, _vector
  mrc p15, 0, r2, c1, c0, 0
  ands r2, r2, #(1 << 13)
  ldreq r1, =0x00000000
  ldrne r1, =0xffff0000
  ldmia r0!, {r2-r8, r10}
  stmia r1!, {r2-r8, r10}
  ldmia r0!, {r2-r8, r10}
  stmia r1!, {r2-r8, r10}
 
  mrs r0, cpsr
  bic r0, #0x80
  msr cpsr_c, r0
 
  ldr r0, =INTC_BASE
  ldr r1, =(1 << 13)
  str r1, [r0, #INTC_EN_REG0]
  ldr r1, =~(1 << 13)
  str r1, [r0, #INTC_MASK_REG0]
 
  ldr r0, =GPIO_BASE
  ldr r1, =0x1000
  str r1, [r0, #(PA + PORT_CFG0)]
  ldr r1, =0x08
  str r1, [r0, #(PA + PORT_DATA)]
 
  ldr r0, =TIMER_BASE
  ldr r1, =256
  str r1, [r0, #TMR0_INTV_VALUE_REG]
  ldr r1, =(7 << 4) | (1 << 1) | 1
  str r1, [r0, #TMR0_CTRL_REG]
  ldr r1, =1
  str r1, [r0, #TMR_IRQ_EN_REG]
  str r1, [r0, #TMR_IRQ_STA_REG]
 
  b .
  .end

完成

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