(FPGA) EPM240T100C5N >> VHDL

Button

---

程式如下：

library ieee;
use ieee.std_logic_1164.all;

entity main is
  port(
    btn: in bit;
    led: out bit_vector(3 downto 0));
end main;

architecture logic of main is
signal cnt:bit_vector(3 downto 0):="0001";

begin
  process(btn) is
  begin
    if (btn'event and btn = '0') then
      cnt<= (cnt rol 1);
    end if;
  end process;

  led<= cnt;
end logic;

腳位


完成

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