EG4S20 >> Verilog

Parallel


main.v

module main(clk, btn, led);
   
input clk;
input btn;
output reg led;
reg [25:0] clk_cnt;
reg [4:0] clk_div;
 
initial begin
  led = 0;
  clk_cnt = 0;
  clk_div = 1;
end
 
always @(posedge clk) begin
  clk_cnt = clk_cnt + 1;
  if (clk_cnt > (24000000 / clk_div)) begin
    clk_cnt = 0;
    led = ~led;
  end
end
 
always @(posedge btn) begin
  clk_div = clk_div + 5;
end
endmodule

main.adc

set_pin_assignment {clk} {location=k14;}
set_pin_assignment {btn} {location=k16;}
set_pin_assignment {led} {location=r3;}

完成


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