Nintendo Entertainment System >> 硬體資訊

CPU

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參考資料：
1. 6502.txt
2. Nesdev_Wiki
3. 6502opcodes.html
4. 6502_instruction_set.html

Register

8 Bits	8 Bits	Description
	A	Accumulator
	X	X Rrgister
	Y	Y Register
	SP	Stack Pointer
	SR	Status Register
PC		Program Counter
	$2000	PPUCTRL
	$2001	PPUMASK
	$2002	PPUSTATUS
	$2003	OAMADDR
	$2004	OAMDATA
	$2005	PPUSCROLL
	$2006	PPUADDR
	$2007	PPUDATA
	$4000	SQ1_VOL, Duty and volume for square wave 1
	$4001	SQ1_SWEEP, Sweep control register for square wave 1
	$4002	SQ1_LO, Low byte of period for square wave 1
	$4003	SQ1_HI, High byte of period and length counter value for square wave 1
	$4004	SQ2_VOL, Duty and volume for square wave 2
	$4005	SQ2_SWEEP, Sweep control register for square wave 2
	$4006	SQ2_LO, Low byte of period for square wave 2
	$4007	SQ2_HI, High byte of period and length counter value for square wave 2
	$4008	TRI_LINEAR, Triangle wave linear counter
	$4009	Unused, but is eventually accessed in memory-clearing loops
	$400A	TRI_LO, Low byte of period for triangle wave
	$400B	TRI_HI, High byte of period and length counter value for triangle wave
	$400C	NOISE_VOL, Volume for noise generator
	$400D	Unused, but is eventually accessed in memory-clearing loops
	$400E	NOISE_LO, Period and waveform shape for noise generator
	$400F	NOISE_HI, Length counter value for noise generator
	$4010	DMC_FREQ, Play mode and frequency for DMC samples
	$4011	DMC_RAW, 7-bit DAC
	$4012	DMC_START, Start of DMC waveform is at address $C000 + $40*$xx
	$4013	DMC_LEN, Length of DMC waveform is $10*$xx + 1 bytes (128*$xx + 8 samples)
	$4014	OAMDMA, Writing $xx copies 256 bytes by reading from $xx00-$xxFF and writing to OAMDATA ($2004)
	$4015	SND_CHN, Sound channels enable and status
	$4016	JOY1, Joystick 1 data (R) and joystick strobe (W)
	$4017	JOY2, Joystick 2 data (R) and frame counter control (W)
	$4018-$401F	APU and I/O functionality that is normally disabled. See CPU Test Mode.

Status

Bit7	6	5	4	3	2	1	0
(S) Sign flag	(V) Overflow flag		(B) Software interrupt flag	(D) BCD	(I)Interrupt enable/disable flag	(Z) Zero flag	(C) Carry flag

Instruction Set

Instruction	Description
ADC	Add Memory to Accumulator with Carry
AND	"AND" Memory with Accumulator
ASL	Shift Left One Bit (Memory or Accumulator)
BCC	Branch on Carry Clear
BCS	Branch on Carry Set
BEQ	Branch on Result Zero
BIT	Test Bits in Memory with Accumulator
BMI	Branch on Result Minus
BNE	Branch on Result not Zero
BPL	Branch on Result Plus
BRK	Force Break
BVC	Branch on Overflow Clear
BVS	Branch on Overflow Set
CLC	Clear Carry Flag
CLD	Clear Decimal Mode
CLI	Clear interrupt Disable Bit
CLV	Clear Overflow Flag
CMP	Compare Memory and Accumulator
CPX	Compare Memory and Index X
CPY	Compare Memory and Index Y
DEC	Decrement Memory by One
DEX	Decrement Index X by One
DEY	Decrement Index Y by One
EOR	"Exclusive-Or" Memory with Accumulator
INC	Increment Memory by One
INX	Increment Index X by One
INY	Increment Index Y by One
JMP	Jump to New Location
JSR	Jump to New Location Saving Return Address
LDA	Load Accumulator with Memory
LDX	Load Index X with Memory
LDY	Load Index Y with Memory
LSR	Shift Right One Bit (Memory or Accumulator)
NOP	No Operation
ORA	"OR" Memory with Accumulator
PHA	Push Accumulator on Stack
PHP	Push Processor Status on Stack
PLA	Pull Accumulator from Stack
PLP	Pull Processor Status from Stack
ROL	Rotate One Bit Left (Memory or Accumulator)
ROR	Rotate One Bit Right (Memory or Accumulator)
RTI	Return from Interrupt
RTS	Return from Subroutine
SBC	Subtract Memory from Accumulator with Borrow
SEC	Set Carry Flag
SED	Set Decimal Mode
SEI	Set Interrupt Disable Status
STA	Store Accumulator in Memory
STX	Store Index X in Memory
STY	Store Index Y in Memory
TAX	Transfer Accumulator to Index X
TAY	Transfer Accumulator to Index Y
TSX	Transfer Stack Pointer to Index X
TXA	Transfer Index X to Accumulator
TXS	Transfer Index X to Stack Pointer
TYA	Transfer Index Y to Accumulator

Opcode

	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	BRK	ORA X, ind				ORA zero	ASL zero		PHP	ORA #	ASL A			ORA abs	ASL abs
1x	BPL rel	ORA ind, Y				ORA zero, X	ASL zero, X		CPC	ORA abs, Y				ORA abs, X	ASL abs, X
2x	JSR abs	AND X, ind			BIT zero	AND zero	ROL zero		PLP	AND #	ROL A		BIT abs	AND abs	ROL abs
3x	BMI rel	AND ind, Y				AND zero, X	ROL zero, X		SEC	AND abs, Y				AND abs, X	ROL abs, X
4x	RTI	EOR X, ind				EOR zero	LSR zero		PHA	EOR #	LSR A		JMP abs	EOR abs	LSR abs
5x	BVC rel	EOR ind, Y				EOR zero, X	LSR zero, X		CLI	EOR abs, Y				EOR abs, X	LSR abs, X
6x	RTS	ADC X, ind				ADC zero	ROR zero		PLA	ADC #	ROR A		JMP ind	ADC abs	ROR abs
7x	BVS rel	ADC ind, Y				ADC zero, X	ROR zero, X		SEI	ADC abs, Y				ADC abs, X	ROR abs, X
8x		STA X, ind			STY zero	STA zero	STX zero		DEY		TXA		STY abs	STA abs	STX abs
9x	BCC rel	STA ind, Y			STY zero, X	STA zero, X	STX zero, X		TYA	STA abs, Y	TXS			STA abs, X
Ax	LDY #	LDA X, ind	LDX #		LDY zero	LDA zero	LDX zero		TAY	LDA #	TAX		LDY abs	LDA abs	LDX abs
Bx	BCS rel	LDA ind, Y			LDY zero, X	LDA zero, X	LDX zero, Y		CLV	LDA abs, Y	TSX		LDY abs, X	LDA abs, X	LDX abs, Y
Cx	CPY #	CMP X, ind			CPY zero	CMP zero	DEC zero		INY	CMP #	DEX		CPY abs	CMP abs	DEC abs
Dx	BNE rel	CMP ind, Y				CMP zero, X	DEC zero, X		CLD	CMP abs, Y				CMP abs, X	DEC abs, X
Ex	CPX #	SBC X, ind			CPX zero	SBC zero	INC zero		INX	SBC #	NOP		CPX abs	SBC abs	INC abs
Fx	BEQ rel	SBC ind, Y				SBC zero, X	INC zero, X		SED	SBC abs, Y				SBC abs, X	INC abs, X

Cycles

Assembly	Opode	Bytes	Cycles
ADC #Immediate	69	2	2
ADC ZeroPage	65	2	3
ADC ZeroPage,X	75	2	4
ADC Absolute	60	3	4
ADC Absolute,X	70	3	4*
ADC Absolute,Y	79	3	4*
ADC (Indirect,X)	61	2	6
ADC (Indirect),Y	71	2	5*
AND #Immediate	29	2	2
AND ZeroPage	25	2	3
AND ZeroPage,X	35	2	4
AND Absolute	2D	3	4
AND Absolute,X	3D	3	4*
AND Absolute,Y	39	3	4*
AND (Indirect,X)	21	2	6
AND (Indirect),Y	31	2	5
ASL A	0A	1	2
ASL ZeroPage	06	2	5
ASL ZeroPage,X	16	2	6
ASL Absolute	0E	3	6
ASL Absolute,X	1E	3	7
BCC Relative	90	2	2*
BCS Relative	B0	2	2*
BEQ Relative	F0	2	2*
BIT ZeroPage	24	2	3
BIT Absolute	2C	3	4
BMI Relative	30	2	2*
BNE Relative	D0	2	2*
BPL Relative	10	2	2*
BRK	00	1	7
BVC Relative	50	2	2*
BVS Relative	70	2	2*
CLC	18	1	2
CLD	D8	1	2
CLI	58	1	2
CLV	B8	1	2
CMP #Immediate	C9	2	2
CMP ZeroPage	C5	2	3
CMP ZeroPage,X	D5	2	4
CMP Absolute	CD	3	4
CMP Absolute,X	DD	3	4*
CMP Absolute,Y	D9	3	4*
CMP (Indirect,X)	C1	2	6
CMP (Indirect),Y	D1	2	5*
CPX #Immediate	E0	2	2
CPX ZeroPage	E4	2	3
CPX Absolute	EC	3	4
CPY #Immediate	C0	2	2
CPY ZeroPage	C4	2	3
CPY Absolute	CC	3	4
DEC ZeroPage	C6	2	5
DEC ZeroPage,X	D6	2	6
DEC Absolute	CE	3	6
DEC Absolute,X	DE	3	7
DEX	CA	1	2
DEY	88	1	2
EOR #Immediate	49	2	2
EOR ZeroPage	45	2	3
EOR ZeroPage,X	55	2	4
EOR Absolute	40	3	4
EOR Absolute,X	50	3	4*
EOR Absolute,Y	59	3	4*
EOR (Indirect,X)	41	2	6
EOR (Indirect),Y	51	2	5*
INC ZeroPage	E6	2	5
INC ZeroPage,X	F6	2	6
INC Absolute	EE	3	6
INC Absolute,X	FE	3	7
INX	E8	1	2
INY	C8	1	2
JMP Absolute	4C	3	3
JMP Indirect	6C	3	5
JSR Absolute	20	3	6
LDA #Immediate	A9	2	2
LDA ZeroPage	A5	2	3
LDA ZeroPage,X	B5	2	4
LDA Absolute	AD	3	4
LDA Absolute,X	BD	3	4*
LDA Absolute,Y	B9	3	4*
LDA (Indirect,X)	A1	2	6
LDA (Indirect),Y	B1	2	5*
LDA #Immediate	A2	2	2
LDA ZeroPage	A6	2	3
LDA ZeroPage,Y	B6	2	4
LDA Absolute	AE	3	4
LDA Absolute,Y	BE	3	4*
LDY #Immediate	A0	2	2
LDY ZeroPage	A4	2	3
LDY ZeroPage,X	B4	2	4
LDY Absolute	AC	3	4
LDY Absolute,X	BC	3	4*
LSR A	4A	1	2
LSR ZeroPage	46	2	5
LSR ZeroPage,X	56	2	6
LSR Absolute	4E	3	6
LSR Absolute,X	5E	3	7
NOP	EA	1	2
ORA #Immediate	09	2	2
ORA ZeroPage	05	2	3
ORA ZeroPage,X	15	2	4
ORA Absolute	0D	3	4
ORA Absolute,X	1D	3	4*
ORA Absolute,Y	19	3	4*
ORA (Indirect,X)	01	2	6
ORA (Indirect),Y	11	2	5
PHA	48	1	3
PHP	08	1	3
PLA	68	1	4
PLP	28	1	4
ROR A	2A	1	2
ROL ZeroPage	26	2	5
ROL ZeroPage,X	36	2	6
ROL Absolute	2E	3	6
ROL Absolute,X	3E	3	7
ROR A	6A	1	2
ROR ZeroPage	66	2	5
ROR ZeroPage,X	76	2	6
ROR Absolute	6E	3	6
ROR Absolute,X	7E	3	7
RTI	4D	1	6
RTS	60	1	6
SBC #Immediate	E9	2	2
SBC ZeroPage	E5	2	3
SBC ZeroPage,X	F5	2	4
SBC Absolute	ED	3	4
SBC Absolute,X	FD	3	4*
SBC Absolute,Y	F9	3	4*
SBC (Indirect,X)	E1	2	6
SBC (Indirect),Y	F1	2	5
SEC	38	1	2
SED	F8	1	2
SEI	78	1	2
STA ZeroPage	85	2	3
STA ZeroPage,X	95	2	4
STA Absolute	80	3	4
STA Absolute,X	90	3	5
STA Absolute,Y	99	3	5
STA (Indirect,X)	81	2	6
STA (Indirect),Y	91	2	6
STX ZeroPage	86	2	3
STX ZeroPage,Y	96	2	4
STX Absolute	8E	3	4
STY ZeroPage	84	2	3
STY ZeroPage,X	94	2	4
STY Absolute	8C	3	4
TAX	AA	1	2
TAY	A8	1	2
TSX	BA	1	2
TXA	8A	1	2
TXS	9A	1	2
TYA	98	1	2

Memory Map

Range	Size	Device
$0000-$07FF	$0800	2KB internal RAM(zero page is $0000-$00FF)
$0800-$0FFF	$0800	Mirrors of $0000-$07FF
$1000-$17FF	$0800	Mirrors of $0000-$07FF
$1800-$1FFF	$0800	Mirrors of $0000-$07FF
$2000-$2007	$0008	NES PPU registers
$2008-$3FFF	$1FF8	Mirrors of $2000-2007 (repeats every 8 bytes)
$4000-$4017	$0018	NES APU and I/O registers
$4018-$401F	$0008	APU and I/O functionality that is normally disabled
$4020-$FFFF	$BFE0	Cartridge space: PRG ROM, PRG RAM, and mapper registers
$6000-$7FFF	$1FFF	Battery Backed Save or Work RAM
$8000-$FFFF	$7FFF	Usual ROM, commonly with Mapper Registers
$FFFA-$FFFB	$0002	NMI vector
$FFFC-$FFFD	$0002	Reset vector
$FFFE-$FFFF	$0002	IRQ/BRK vector

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