(ARM Cortex-A7) V3S (Lichee Pi Zero) >> Assembly
Watchdog
參考資訊：
1. pdf
方塊圖
Registers
IRQ Register
Control、Configuration
Mode
main.s
.global _start
.equ GPIO_BASE, 0x01c20800
.equ TIMER_BASE, 0x01c20c00
.equ PG, (0x24 * 6)
.equ TMR_IRQ_STA_REG, 0x04
.equ WDOG_IRQ_EN_REG, 0xa0
.equ WDOG_IRQ_STA_REG, 0xa4
.equ WDOG_CTRL_REG, 0xb0
.equ WDOG_CFG_REG, 0xb4
.equ WDOG_MODE_REG, 0xb8
.equ CFG0, 0x00
.equ DATA, 0x10
.arm
.text
_start:
.long 0xea000016
.byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
.long 0, __spl_size
.byte 'S', 'P', 'L', 2
.long 0, 0
.long 0, 0, 0, 0, 0, 0, 0, 0
.long 0, 0, 0, 0, 0, 0, 0, 0
_vector:
b reset
b .
b .
b .
b .
b .
b .
b .
reset:
ldr r0, =GPIO_BASE
ldr r1, =1
str r1, [r0, #(PG + CFG0)]
ldr r1, =1
str r1, [r0, #(PG + DATA)]
ldr r2, =TIMER_BASE
ldr r3, =(0 << 4) | (1 << 0)
str r3, [r2, #WDOG_MODE_REG]
ldr r3, =(2 << 0)
str r3, [r2, #WDOG_CFG_REG]
ldr r3, =(0xa57 << 1) | (1 << 0)
str r3, [r2, #WDOG_CTRL_REG]
ldr r4, =(1 << 0)
0:
ldr r3, [r2, #WDOG_IRQ_STA_REG]
tst r3, #(1 << 0)
beq 0b
str r3, [r2, #WDOG_IRQ_STA_REG]
ldr r3, =(0xa57 << 1) | (1 << 0)
str r3, [r2, #WDOG_CTRL_REG]
eor r1, r4
str r1, [r0, #(PG + DATA)]
b 0b
.end
完成
