TRIMUI SMART >> Assembly
HS Timer0
參考資訊：
1. pdf
CCU位址
AHB1暫存器
HSTMR_GATING
HSTMR_RST
HS Timer位址
IRQ
Control
Interval Value
Current Value
main.s
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 | .global _start .equ CCU_BASE, 0x01c20000 .equ GPIO_BASE, 0x01c20800 .equ HSTMR_BASE, 0x01c60000 .equ PG, (0x24 * 6) .equ CFG1, 0x04 .equ DATA, 0x10 .equ PLL_CPU_CTRL_REG, 0x00 .equ CPU_AXI_CFG_REG, 0x50 .equ AHB1_APB1_CFG_REG, 0x54 .equ BUS_CLK_GATING_REG0, 0x60 .equ BUS_SOFT_RST_REG0, 0x2c0 .equ HS_TMR_IRQ_STAS_REG, 0x04 .equ HS_TMR0_CTRL_REG, 0x10 .equ HS_TMR0_INTV_LO_REG, 0x14 .equ HS_TMR0_INTV_HI_REG, 0x18 .equ HS_TMR0_CURNT_LO_REG, 0x1c .equ HS_TMR0_CURNT_HI_REG, 0x20 .arm .text_start: .long 0xea000016 .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0' .long 0, __spl_size .byte 'S', 'P', 'L', 2 .long 0, 0 .long 0, 0, 0, 0, 0, 0, 0, 0 .long 0, 0, 0, 0, 0, 0, 0, 0 _vector: b reset b . b . b . b . b . b . b .reset: ldr r0, =CCU_BASE ldr r1, =(1 << 31) | (12 << 8) str r1, [r0, #PLL_CPU_CTRL_REG]1: ldr r1, [r0, #PLL_CPU_CTRL_REG] tst r1, #(1 << 28) beq 1b ldr r1, =(3 << 16) str r1, [r0, #CPU_AXI_CFG_REG] ldr r1, =(2 << 12) str r1, [r0, #AHB1_APB1_CFG_REG] ldr r1, =(1 << 19) str r1, [r0, #BUS_CLK_GATING_REG0] str r1, [r0, #BUS_SOFT_RST_REG0] ldr r0, =GPIO_BASE ldr r1, =0x11111111 str r1, [r0, #(PG + CFG1)] ldr r1, =0xffff str r1, [r0, #(PG + DATA)] ldr r2, =HSTMR_BASE ldr r3, =408000000 str r3, [r2, #HS_TMR0_INTV_LO_REG] str r3, [r2, #HS_TMR0_CURNT_LO_REG] ldr r3, =0x00000000 str r3, [r2, #HS_TMR0_INTV_HI_REG] str r3, [r2, #HS_TMR0_CURNT_HI_REG] ldr r3, =(1 << 1) | (1 << 0) str r3, [r2, #HS_TMR0_CTRL_REG] ldr r4, =(1 << 10)1: ldr r3, [r2, #HS_TMR_IRQ_STAS_REG] tst r3, #(1 << 0) beq 1b str r3, [r2, #HS_TMR_IRQ_STAS_REG] eor r1, r4 str r1, [r0, #(PG + DATA)] b 1b .end |
完成
